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ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 1 features ? includes dialer, speech, and ringer circuit replacing two or more ics. ? single board design meets multiple ptt requirements. ? pause and mute functions. ? adjustable flash duration. ? 32digit last number redial. ? selectable tone/pulse dialing. ? 13 to 70hz ring frequency detection. ? operating range from 15 to 100ma. ? compatible with icm7101d/icm7102. overview ICM7102B is a single chip telephone cmos integrated circuits that meets multiple ptt requirements, allowing phone manufacturers to have single board design for various countries. this reduces inventory and simplify manufacturing processes. ICM7102B integrates dialer, speech, and ringer circuits. the integration reduces component counts, hence increases product reliability. typical application circuit typical application circuit is as specified in appe ndix a. package 28lead soic figure 1 : 28lead soic package 1 agnd 2 vdd 3 vddi 4 gnd 5 txo 6 vl 7 llc 8 fopt0 9 mfl0 10 hs_dpb 11 osc1 28 stb 27 rxi 26 rxo 25 ci 24 m1 23 m2 22 r1 21 r2 20 r3 19 r4 18 c1b 12 osc2 17 c2b 7102 soic 13 rgd 16 c3b 14 mo 15 c4b 1 agnd 1 agnd 2 vdd 2 vdd 3 vddi 3 vddi 4 gnd 4 gnd 5 txo 5 txo 6 vl 6 vl 7 llc 7 llc 8 fopt0 8 fopt0 9 mfl0 9 mfl0 10 hs_dpb 10 hs_dpb 11 osc1 11 osc1 28 stb 28 stb 27 rxi 27 rxi 26 rxo 26 rxo 25 ci 25 ci 24 m1 24 m1 23 m2 23 m2 22 r1 22 r1 21 r2 21 r2 20 r3 20 r3 19 r4 19 r4 18 c1b 18 c1b 12 osc2 12 osc2 17 c2b 17 c2b 7102 soic 13 rgd 13 rgd 16 c3b 16 c3b 14 mo 14 mo 15 c4b 15 c4b ICM7102B soic
ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 2 pin description pin no symbol description 1 agnd analog ground 1.4v regulated voltage output. used by internal ampli fiers. external capacitor about 100uf should be connected to this pin. 2 vdd regulated supply voltage when hs_dpb pin is high, the vdd pin is regulated to 3.1v, and the input power is extracted from vddi pin. when hs_dpb is low , vdd should be externally powered and it must not fall below 1.0v to retain the redial memory. most internal circuits are powered by vdd pin. 3 vddi supply input voltage power for the chip is extracted from this vddi pin. s ee also vdd pin description. at steady state, vddi is regulated to 3.5 v by use of external pnp transistor whose base terminal is connected to the txo pin. see typical application circuit. the external pnp transistor als o functions to drain the excess line current. 4 gnd ground 5 txo transmit output transmit output is to be connected to external pnp tra nsistor (typically medium power pnp) for the modulation of line voltage an d for shorting the line during make period of pulse dialing. see the typic al application circuit. the external pnp transistor also functions to drain the excess line current. 6 vl line voltage if lineloss compensation (llc) scheme is not used, then this pin can be shorted to gnd. if llc scheme is used, then this pin i s used to sense the line current. the sense resistor (r11 in typical applicatio n circuit) must be 30 ohm for the llc scheme to work properly. the receive and transmit gains are adjusted according to the sensed current and the chosen ll c scheme. see also description on line loss compensation section. since vl pin will typically experience high transient voltage, it is ad visable to properly add external protection circuit to suppress the high tran sient voltage which can damage the pin. 7 llc line loss compensation line loss compensation scheme options: llc=gnd no llc scheme. llc=agnd low llc scheme. llc=vdd high llc scheme. the receive and transmit gains are adjusted according to the sensed current and the chosen llc scheme. see description on line loss compensation section. 8 fopt0 flash option flash duration options: gnd (logic 0) C 300ms flash duration. vdd (logic 1) C 600ms flash duration. 9 mfl0 dtmf option transmitted dtmf level options: gnd (logic 0): typical 8/10db. vdd (logic 1): typical 6/8db. 10 hs_dpb hook switch input and dial pulse outp ut when offhook, this pin needs to be pulled high (by th e hook switch) to activate the speech and dialer circuits. when onhook this pin needs to be pulled low to activate ringer circuit and deactivate sp eech and dialer circuits. during pulse dialing (while offhook, and pulse diali ng mode is chosen), this pin is pulled low during linebreak periods.
ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 3 11 osc1 oscillator input 3.58mhz ceramic resonator input. 12 osc2 oscillator output 3.58mhz clock output. can be used to drive other few h igh impedance inputs. 13 rgd ring detection input input for ring frequency detection. active when hs_dpb= low. when pulses with frequency between 13hz and 70hz are detected on this p in, ring melody is generated on the mo pin. 14 mo melody output open drain output. when ring signal is detected on th e rgd pin, ring melody pulses are generated on this pin. 15 16 17 18 c4b c3b c2b c1b keypad columns keypad column inputs. when a column input pin is shor ted to a row output pin, appropriate dtmf signal is generated. this dtmf s ignal complies with ccitt recommendation. for example, when r1 and c1b ar e shorted (when button #1 is pressed), dtmf signal of frequency 697hz + 1209hz is generated and transmitted thru txo pin. 19 20 21 22 r4 r3 r2 r1 keypad rows keypad rows. logic pulses are generated on these pins to scan user input. see also keypad column pins. during poweronreset, these pi ns are also used to determine various dialing modes. see description on dia ling function section. 23 24 m1 m2 microphone inputs input for electret microphone. m1 connects to invertin g input of internal differential amplifier via a resistor. m2 connects to the noninverting input via a resistor. 25 ci complex impedance and ac impedance input placing resistor between ci and agnd pins adjusts the ac impedance. if ci pin is left floating the typical ac impedance is 1000 ohm (when current sense resistor (r11) is 30 ohm). 26 rxo receive d audio amplifier output received audio amplifier output. rxo can drive a typic al 120ohm dynamic earpiece speaker. 27 rxi received audio amplifier input noninverting input for internal received audio differen tial amplifier. rxi connects to the amplifier via an internal resistor. rxi also internally connects to the feedback path of the circuitry that determines t he ac impedance. 28 stb side tone balance input inverting input for internal received audio different ial amplifier. stb connects to the amplifier via an internal resistor.
ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 4 functional description system startup ICM7102B generates internal poweronreset when vdd reaches around 1.5v. poweron reset appropriately initiates the system to a known initial state. note that the initial ramp up of vdd could come from external ringer interface circuit, or it could come from internal regulator when the system goes offhook. as long as hs_dpb pin stays low, ICM7102B operates in shutdown mode with only the ringer circuitry being activated to monitor the incoming ringing signal. oscillator all the timing of ICM7102B is based on a clock frequency of 3.58 mhz. a crystal or ceramic resonator of this frequency should be connected to osc1 and osc2 pins. care has to be taken in selecting this components since in practise minor deviations from the nominal frequency may occur due to the characteristics of the oscillator. it is recommended to connect a small value capacitors ( 47pf) in parallel with the oscillator to ensure proper startup and operation at the nominal frequency. tone ringer the tone ringer of ICM7102B consists of ring detection circuit and melody generator circuit. these circuits are active when the system is in onhook state (hs_dpb pin is low). ring detection circuit ring detection circuit will assures the signal present on rgd pin input is valid. the signal is considered valid if it has frequencies between 13hz and 70hz. this signal is monitored continuously and the ring melody is turned on/off accordingly. melody generator once the valid ring signal is detected on the schmitttriggered ring detection pin (rgd) and the signal is present for about 75 ms continously, the melody generator will be enabled, generating ring tones of 1250hz and 1600hz on the mo pin. note that mo is an opendrain pin. speech network the speech network of ICM7102B consists of a transmitter and a receiver path, side tone cancellation and line loss compensation. the speech network is activated as soon as the phone goes offhook (i.e. when hs_dpb pin goes high). at the same time the ringer circuitry is deactivated. transmit the typical total transmit gain from microphone input (m1/m2 pins) to the vddi pin is 35db when the ac impedance is 600. receive the typical total receive gain from the line voltage to rxo pin is 5db when the ac impedance is 600. side tone cancellation as shown in the typical application circuit in appendix a, side tone cancellation can be achieved best by balancing the whitestone bridge comprised of r11, r12, r13+r14//c6, and the line impedance. line loss compensation llc pin input level is scanned as the phone goes offhook (i.e. as hs_dpb pin goes high). at the same time, the loop current level is sensed and determined. if llc=0, no compensation scheme is in effect. if llc=agnd, low compensation scheme is in effect. transmit and receive gains are reduced by as much as 6db when the loop current exceeds 50ma. if llc=vdd, high compensation scheme is in effect. transmit and receive gains are reduced by as much as 6db when the loop current exceeds 75ma. ac impedance (z ac ) placing a resistor, r zac between ci and agnd pins adjusts the ac impedance. if r zac is not
ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 5 present, the typical ac impedance is 1000. refer to figure 2 for the equivalent test circuit. r zac =82k typically sets the ac impedance to 600, while r zac =47k typically sets the ac impedance to 470. please note that the overall system ac impedance also depends on the whole system circuit. dtmf signal level dtmf signal level can be selected by setting mfl0 pin as follow: mfl0 typical dtmf level ( r zac =47k; z ac = 470 ) 0 low, typical 8/ 10db 1 high, typical 6/ 8db dialing functions keypad arrangement is as shown in the typical application circuit in appendix a. dialing modes are selectable using the pullup/pull down resistors connected to the row inputs. as soon as the phone goes offhook (i.e when hs_dpb pin goes high), voltage levels on keypad row inputs (r1 thru r4) are first scanned to determine the operating mode as follow: pin functio n level C mode r1 dialing mode 0 C mf mode 1 C pulse mode r2 pulse period 0 C 10 pps 1 C 20 pps r3 make/break ratio 0 C 40/60 1 C 33/67 r4 dtmf option 0 C 82ms/82ms 1 C 82ms/160ms valid keys ICM7102B has a total of 16 valid keys. it scans the keys by asserting known state on pins r1, r2, r3, and r4 in sequence, and check which column (pins c1b, c2b, c3b, c4b) is shorted to which row. the following specify the combinations: c1 b c2 b c3 b c4 b r1 1 2 3 pause r2 4 5 6 mute r3 7 8 9 flash r4 * 0 # lnr dtmf tones the dtmf tone generator creates 12 tones in compliance with ccitt recommendation. there are two group of frequencies of dtmf tones. the low group depends on the keys row, while the high group depends on the keys column as illustrated in the following table: c1 b c2 b c3 b low freq r1 1 2 3 697 hz r2 4 5 6 770 hz r3 7 8 9 852 hz r4 * 0 # 941 hz high freq 1209 hz 1336 hz 1477 hz last number redial (lnr) the last number redial (lnr) is a facility of ICM7102B to allow resignalling of the last manually dialled number without keying in all digits again. the lnr is repeatable after each offhook. a manually entered number is stored in internal 32digit ram. vdd shall not fall below 1.0v during onhook state to properly retain the data in the memory. flash ICM7102B asserts line break (pulls down hs_dpb pin) when flash key is depressed. the flash duration depends on the input levels of fopt0 pin as follow: fopt0 flash duration 0 300 ms 1 600 ms mute ICM7102B inhibits mic (m1/m2) input when mute key is depressed. depressing the key again toggles the mute function. pause ICM7102B pauses (no dialing and microphone is muted) for 2.2 seconds when pause key is depressed.
ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 6 absolute maximum rating symbol parameter value unit vddi supply l ine voltage 0.3 to 7.0 v v in_ digital input voltage 0.3 to 7.0 v t stg storage temperature 5 5 to +150 o c t sol soldering temperature 300 o c note 1: stress greater than those listed under abso lute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operati on of the device at these or any other conditions a bove those indicated in the operational sections of this specification is not i mplied. exposure to absolute maximum rating conditi ons for extended periods may affect reliability. operating range range ambient temperature commercial 25 o c to 70 o c dc characteristics (i line = 15ma unless otherwise specified) symbol parameter test conditions min typ max unit v ddi regulated line voltage i line : 13ma to 100ma 3.2 3.5 3.8 v vdd regulated supply 3. 1 v agnd regulated reference 1. 3 1. 4 1. 5 v i dd operating current speech mode 2.5 5.5 ma dialing mode 4 .0 5.5 ma ring mode 0.3 ma i ol output current sink hs_dpb, mo; v ol = 0.4v 1.5 ma vil inpu t voltage low hs_ dpb, rgd ; t a =25 o c 0.0 1.5 v vih input voltage high hs_ dpb, rgd ; t a =25 o c 2. 2 6.0 v ac characteristics (i line = 15ma, frequency = 800hz, unless otherwise specif ied) symbol parameter test conditions min typ max unit transmit (tx) g tx transmit gain llc=gnd , z a c = 600 3 1 .5 3 3 3 2 .5 db thd distortion v l < 0.5 v rms 2 % z in m1,m2 input impedance 20 k g mute mute attenuation mute activated 8 0 db v in m1,m2 input voltage range 2.8 v peak receive (rx) g rx receive gain llc=gnd, z ac = 600 , volume=reset 4.0 5.0 6.0 db thd distortion v rxi < 0.5 v rms 2 % z in rxi input impedance 8 k v in rxi input voltage range 2.8 v peak
ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 7 side tone (st) g st side tone cancellation llc=gnd, z a c = 600 2 3 db z in stb input impedance 8 0 k v in st b input voltage range 2.8 v peak output driver (bjt) v in pnp input voltage range 2.8 v peak v tx pnp dynamic range 2.8 v peak return loss rl return loss z l ine =6 00 , z a c = 600 18 db keyboard t d key debounce time 64 ms hs/dpb input t hs l low to high debounce going off hook 15 ms t hs h high to low debounce going on hook 240 ms tone ringer v mo melody output pdm t md melody delay 10 ms f1 frequency 1 1250 hz f2 frequency 2 1600 hz t dt detection time ring freq = 20hz 50 80 ms f mi n min. detection freq. 13 hz f max max. detection freq. 70 hz dtmf f frequency deviation note 2 0.31 +0.75 % t td tone duration note 1 80 82 84 ms t itp inter tone pause note 1 80 82 84 ms note 1: the values are valid during automatic diali ng and are minimum values during manual dialing, i. e. the tones will continue as long as the key is depressed. note 2: this does not include the frequency deviati on of the ceramic resonator.
ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 8 figure 2 : equivalent test circuit

ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 10 appendix b: package information 28-lead sop (unit: inches)
ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 11
ICM7102B l ow c ost s ingle c hip t elephone ic rev. 2.7 icmic reserves the right to change the spe cifications without prior notice 12 disclaimer the information contained herein is current as of t he date of publication; however, delivery of this document shall not under any circumstances create a ny implication that the information contained herein is correct as of any time subsequent to such date. icmic reserves the right to make changes without notification, even if such changes would re nder information contained herein inaccurate or incomplete. icmic makes no representation or warran ty that any circuit designed by reference to the information contained herein, will function without errors and as intended by the designer.

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